{"product_id":"principles-of-verifiable-rtl-design","title":"Principles of Verifiable Rtl Design:","description":"\u003cp\u003eNorwell, Mass.: Kluwer Academic Publishers, 2000. First edition (presumed; no earlier dates stated). Purple octavo; xvii, 253 p, b\u0026amp;w illus; 24 cm. Faint rubbed fold to spine head \u0026amp; foot \u0026amp; folds, barely rubbed corners, else near fine(+). Hardcover. ISBN: 0792377885\u003c\/p\u003e\u003cp\u003eContents: Register Transfer Level --; What is It? --; Verifiable RTL --; Applying Design Discipline --; The Verification Process --; Specification Design Decomposition --; High-Level Design Requirements --; Block-Level Specification and Design --; RTL Implementation --; Synthesis and Physical Design --; Functional Test Strategies --; Deterministic or Directed Test --; Random Test --; Transaction Analyzer Verification --; Chip Initialization Verification --; Synthesizable Testbench --; Transformation Test Strategies --; Coverage, Events and Assertions --; Coverage --; Ad-hoc Metrics --; Programming Code Metrics --; State Machine and Arc Coverage Metrics --; User Defined Metrics --; Fault Coverage Metrics --; Regression Analysis and Test Suite Optimization --; Event Monitors and Assertion Checkers --; Events --; Assertions --; Assertion Monitor Library Details --; Event Monitor and Assertion Checker Methodology --; Linting Strategy --; Implementation Considerations --; Event Monitor Database and Analysis --; RTL Methodology Basics --; Simple RTL Verifiable Subset --; Linting --; Linting in a design project --; Lint description --; Project Oriented --; Linting Message Examples --; Object-Based Hardware Design --; OBHD and Simulation --; OBHD and Formal Verification --; OBHD and Physical Design --; OBHD Synthesis --; OBHD Scan Chain Hookup --; A Text Macro Implementation --; RTL Logic Simulation --; Simulation History --; First Steps --; X, Z and Other States --; Function and Timing --; Gate to RTL Migration --; Acceleration and Emulation --; Language Standardization. Integrated circuits -- Very large scale integration -- Computer-aided design.\u003c\/p\u003e","brand":"Bening, Lionel; Foster, Harry","offers":[{"title":"Default Title","offer_id":46055933247746,"sku":"23856.0","price":14.0,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0675\/4412\/1602\/files\/holder_3_474ae1f6-8941-4a19-a36f-c3512e6e58de.jpg?v=1744091514","url":"https:\/\/bibliope.com\/products\/principles-of-verifiable-rtl-design","provider":"Bibliope","version":"1.0","type":"link"}